发明名称 MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PURPOSE: To provide a highly practical method, which uses grinding/polishing equipment used in many chip manufacturing equipment, so as to obtain an extremely flat wafer at a relatively low cost. CONSTITUTION: Oxide layers 3 and 4 are formed on the major planes of a handle wafer 2. An operation wafer 1 is bonded on the handle wafer 2 in insulating condition, and a bonded wafer 5 having the operation wafer 1, the handle wafer 2 and an exposed oxide layer 4 is formed. The operation wafer 1 is thinned to a prescribed thickness using the oxide layer 4 as a reference flat plane, and both the major planes of the bonded water 5 are polished. Generally, the planes are polished by using an etching material which selectively removes the operation wafer 1 from the oxide layers 3 and 4.
申请公布号 JPH06104153(A) 申请公布日期 1994.04.15
申请号 JP19930056401 申请日期 1993.02.23
申请人 AMERICAN TELEPH & TELEGR CO <ATT> 发明人 UIRIAMU GURAHAMU IISUTAA;RICHIYAADO EICHI SHIYANAMAN SAADO
分类号 H01L21/02;H01L21/304;H01L21/306;H01L21/762;H01L27/12;(IPC1-7):H01L21/02 主分类号 H01L21/02
代理机构 代理人
主权项
地址