发明名称 |
BAND COMPRESSION SIGNAL PROCESSOR |
摘要 |
PURPOSE:To improve the picture quality in a high speed reproduction mode by adding overhead data respectively to the variable length code of a refresh block and the variable length code of a non-refresh block so as to from a macro block. CONSTITUTION:A luminance signal Y and chrominance signals U,V fed to input terminals 27-29 are combined by a block processing circuit 30 and the result is fed to a subtraction circuit 12 and a motion evaluation circuit 13 as an input video signal from an input terminal 11, and a video code subjected to a band compression coding is outputted from a variable length coding circuit 16. Then in-frame signal processing is applied synchronously to a signal in b-sets of picture areas among a-sets of areas at every frame synchronously with f-frames (f is an integer being >=2) by the refresh coding processing. Then overhead data representing the content of a variable length code are respectively added to the variable length code of a refresh block and the variable length code of a non-refresh block so as to form a macro block. |
申请公布号 |
JPH06197312(A) |
申请公布日期 |
1994.07.15 |
申请号 |
JP19930172073 |
申请日期 |
1993.06.21 |
申请人 |
TOSHIBA CORP |
发明人 |
NIIMURA KAZUHARU;MAIKERU CHINBAAGU |
分类号 |
H03M7/40;G06T9/00;H04N5/7826;H04N5/783;H04N5/92;H04N7/26;H04N7/30;H04N7/32;H04N7/50;H04N9/804;H04N9/877;(IPC1-7):H04N5/92;H04N7/133;G06F15/66;H04N7/137 |
主分类号 |
H03M7/40 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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