发明名称 ASYNCHRONOUS TRANSFER MODE SWITCH
摘要 <p>PURPOSE:To improve the throughput of the switch by reducing the probability of cell collision. CONSTITUTION:A clock generating circuit 6 generates a high speed clock signal at a speed being a multiple of (m) of a write clock signal of an input buffer 30j, the input buffer 30j reads a cell written in any of m-sets of cell read timings based on a read control signal and a high speed clock signal from a read control section 10 and executes exchange of a switch network 5 and write of an output buffer 40j based on the high speed clock signal.</p>
申请公布号 JPH06205483(A) 申请公布日期 1994.07.22
申请号 JP19920348776 申请日期 1992.12.28
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 GENDA KOICHI;YAMANAKA NAOAKI
分类号 H04Q3/52;H04Q11/04;(IPC1-7):H04Q11/04;H04L12/48 主分类号 H04Q3/52
代理机构 代理人
主权项
地址