| 摘要 |
first and second reset circuits; first and second microprocessors having respective reset input terminals, respective reset output terminals, data synchronizing signal input and output terminals, respective clock pulse receiving terminals, respective data input terminals and respective data output terminals; and first and second bias resistors respectively connected between the first and second reset circuits and the reset input terminals of first and second microprocessors, thereby automatically performing a reset operation in an apparatus using two or more microprocessors.
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