发明名称 |
BOOTSTRAP ADDRESS DECODER |
摘要 |
PURPOSE: To supply a self-clocked signal which bootstraps a work line in a very short period. CONSTITUTION: An address signal generated from address bits A1 and A2 and clock signalsϕY andϕZ are inputted to each clock generator 20. A bootstrap enable signal BEBAR outputted from a row address decoder 22 is inputted also to each clock generator 20. Signalsϕ1 toϕ4 outputted from clock generators 20 are inputted to the row address decoder 22. An address signals generated from address bits A3 to A8 and a clock signalϕX are inputted also to the row address decoder 22. The row address decoder 22 selectively outputs work line signals WL0 to WL255.
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申请公布号 |
JPH06243681(A) |
申请公布日期 |
1994.09.02 |
申请号 |
JP19940019391 |
申请日期 |
1994.02.16 |
申请人 |
NITTETSU SEMICONDUCTOR KK;UNITED MEMORIES INC |
发明人 |
KIMU SHII HAADEII;KENISU JIEI MOBUREI |
分类号 |
G11C11/407;G11C8/10;(IPC1-7):G11C11/408 |
主分类号 |
G11C11/407 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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