| 摘要 |
PURPOSE:To enable correct register interference control to be performed and to prevent interruption responsiveness from being damaged by guaranteeing the dependence relation of data even when interruption is present. CONSTITUTION:When a preceding instruction is completed at the time of interlocking, an SCB register for indicating being-used/unused is reset (indicates an unused state). When the register number coincides with the number of a register to be used, RC0-RER-BUSY, SRC1-REG-BUSY and WRITE-REG-BUSY signals indicating that the register is being used are negated, the suppression of D-STAGE-RELEASE signals is cancelled and an execution stage is proceeded. In such a manner, a source operand waits to be reloaded by the preceding insturction and the latest data can be read. Or, by performing execution after waiting for the completion of reloading by the preceding instruction, the order of the write of results is guaranteed. |
