| 摘要 |
An arithmetic unit rapidly performs an XY+B floating point operation and yields a result equivalent to truncation of the product of X and Y before adding to B. Standard circuitry produces partial products from multiplier X and multiplicand Y, and a standard adder adds the partial products to yield a sum vector and a carry vector. Meanwhile, other circuitry predicts whether a most significant digit of a sum of the sum vector and the carry vector is zero or nonzero, based on less than all bits of the multiplier X and the multiplicand Y. If the most significant digit is certainly not equal to zero, a multiplexing circuit passes to a second adder a most significant N digits of the sum vector, a most significant N digits of the carry vector, a carry bit resulting from addition an (N-1)th most significant digit and lesser significant digits of the sum vector with an (N+1)th most significant digit and less significant digits of the carry vector, and an operand B. If the most significant digit is certainly equal to zero, then the multiplexing circuitry passes to the second adder a most significant N+1 digits of the sum vector, a most significant N+1 digits of the carry vector, a carry bit resulting from the addition of an (N+2)th most significant digit and less significant digits of the sum vector with an (N+2)th most significant digit and lesser significant digits of the carry vector, and the operand B.
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