| 摘要 |
A BiMIS logic circuit includes a first bipolar junction transistor (BJT), a second BJT, a P-channel MIS transistor (PMIS), and an N-channel NMIS transistor (NMIS). A node between the first and second BJTs is connected to a first output terminal, and a node between the PMIS and the NMIS is connected to a second output terminal. When the potentials which cause the PMIS to turn ON and the NMIS to turn OFF are applied, a potential at the second output terminal rises to the power supply potential. The potential at the first output terminal assumes a potential lower than the power supply potential by a turn-on voltage (VF) of the BJT. When the potentials which cause the NMIS to turn ON and the PMIS to turn OFF are applied, the second output terminal and a node between the NMIS and the second BJT are caused to become conductive whereby the potential at the second output terminal falls and the potential at the node rises and both the potentials are equalized. Here, the second BJT turns ON and the potential at the first output terminal falls. The base current supplied to the second BJT gradually ceases and the second BJT turns OFF accordingly. Since the base potential of the BJT at an output stage is always in the neighborhood of VF, it is possible to cause the second BJT to turn ON or OFF by a minute change in the base current. Thus, a high speed performance is ensured even under a low power supply voltage.
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