Method and apparatus for a bus transceiver incorporating a high speed binary data transfer mode with a ternary control transfer mode having a full duplex, dominant logic transmission scheme

摘要

The present invention provides a bus transceiver incorporating a high speed, binary transfer mode for the half-duplex transfer of data signals with a ternary control transfer mode having a full duplex dominant logic transmission scheme for the full duplex transfer of control signals. In one embodiment of the present invention, the above-noted transfer modes are implemented in a bus architecture which includes at least a first communications node coupled to a second communications node via a twisted pair, serial bus. Each node comprises first transceiver and second transceivers having a differential driver for driving on the bus signal states comprising first and second signal states having equal current amplitudes opposite in sign and a third signal state having approximately a zero current amplitude, a high speed binary receiver for receiving high speed data signals during data transfer phases and a ternary receiver for receiving control signals during control transfer phases. The ternary receiver comprises two binary receivers for detecting resultant current amplitudes created on the bus during simultaneous driving of control signals by the nodes during the control transfer phases and logic means for combining the resultant current amplitudes on the bus with the signal states driven by the local transceiver to output reconstructed control signals representing the control signals driven on the bus by the corresponding transceiver. Furthermore, both transceivers further include a preemptive signaling receiver for the detection of preemptive control messages which act to terminate the data transfer phases upon receipt of the message so that higher priority control transfers may take place.