ARRAY CLOCK GENERATOR CIRCUIT

摘要

PURPOSE: To operate a high speed SRAM macro with a short-cycle time system by forming all clock signals which are driven by an input clock signal and which are required for the proper operation of ABIST mode. CONSTITUTION: The multiplexer 41 of an array clock generator circuit 40 is controlled by a control signal STDSO from ABIST unit, and enables the properly structured digital programming of the circuit 40 in accordance with a selected ABIST sub-mode. A chopper circuit 28 forms a CACG signal on the basis of the input signal of a terminal 42-1, and gated by a CNOOP signal in an AND gate 17. When the CNOOP signal is high, the CACG clock signal and a CSACG signal are obtained. In addition, with a clock signal SACG formed from an AND gate 23, a clock signal BACG is formed by a circuit 33'.