| 摘要 |
The circuit includes two P-channel MOSFET's (Q21,Q22) having drains connected to bit lines (B,/B), sources connected to Vcc power line, and gates for receiving a write enable signal (WE) to clamp the bit line voltage upon data-reading, and two P-channel MOSFET's (Q23,Q24) having drains connected to the bit lines (B,/B), sources connected to the Vcc power line, and gates cross-connected to the opposite bit lines (/B,B) respectively to interrupt the DC current upon data-writing, thereby interrupting the DC current upon data-writing without increasing the number of MOSFET.
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