| 摘要 |
PURPOSE: To enable a speed test of a plurality of data propagation paths of an integrated circuit device having a clock buffer in an AC test of a digital integrated circuit by a test device having low band width. CONSTITUTION: An input storage means 51 which receives test data from an automatic test device 20 and supplies input data to a data propagation path and an output storage means 53 which stores output of the data propagation path are provided. These input and output storage means 51, 53 and an internal register in the data propagation path are clocked by alternate single cycle of a first clock which can be delayed arbitrarily and a second clock which corresponds to desired test speed. The first clock is used in the transmission of data among the automatic test device 20 and the input storage means 51 and the output storage means 53 to test whether delay in combined logic circuit nets 21a, 21b, 21c is smaller than or equal to a period of the second clock. |
