DRAM Semiconductor memory operated by external clock pulse signal

摘要

The memory includes a buffer where data is held in synchronism with an external clock pulse signal (105) to safeguard a preset delay time period. A control signal ( PI TRST) is released in synchronism with the clock pulse signal during a preset time period. A stop controller stops a control signal during a given time, that would be free, in synchronisation with the clock pulse. A data output driver (95) receives the output signal of the data buffer and is controlled by the output signal of the buffer control. To the data output driver is coupled a data output device. Pref. the control signal is synchronised with the clock pulse, preceding the clock pulse handling the data according to the clock pulse signal frequency.