| 摘要 |
PROBLEM TO BE SOLVED: To provide a system that can consider and compensate for expected process variations during design and verification processes so that layout can be made more effective and easier to manufacture.SOLUTION: This invention relates to a system for analyzing integrated circuit layout and design by calculating variations of a plurality of objects to be created on a semiconductor wafer as a result of different processing conditions. The variations are analyzed to determine individual feature failures or to rank layout design by influence to the variations caused during processing. In one embodiment, the variations are represented by PV-bands having an inner edge that determines the smallest area in which an object will always print and an outer edge that determines the largest area in which the object will print under specific process conditions.SELECTED DRAWING: Figure 15 |
