| 摘要 |
<p>A robust family of pre-conditioned (90, 100) complementary CMOS logic elements (72) using scaled MOSFET's (86, 88) and a single clock phase (70) which may be easily interconnected to form high speed logic networks (68). The family includes both N-type and P-type pre-conditioned logic elements (90, 100) using a skewed complementary CMOS structure to achieve low power and high speed. The logic elements achieve next generation CMOS performance yet are manufactured using present day processes and equipment. Logic element implementation is described in detail. A method for scaling the MOSFET's according to the present invention is provided, and several routing methods for reducing interconnection cross-talk are set forth.</p> |
