发明名称 NONVOLATILE SEMICONDUCTOR MEMORY
摘要 <p>PURPOSE: To obtain an EEPROM having such structure and operation as fluctuation in the threshold voltage can be suppressed after writing and erasure without requiring any verify circuit. CONSTITUTION: In an EEPROM wherein a p-well 3 is formed on an n-well 2 formed on a p-type substrate 1 and a plurality of memory cells are arranged in the p-well 3, the memory cell comprises source-drain diffusion layers 4a, 4b formed in the p-well 3 add a floating gate 6 and a control gate laminated on a channel between the source and drain. A data is rewritten by delivering or receiving charges between the floating gate 6 and the p-well 33. A positive voltage is applied to the control gate 8 and 0V is applied between the source and drains 4a, 4b. A negative potential is applied to the p-well 3 to form a depletion region and then a negative potential is applied to the n-well 2 thus injecting carriers into the p-well 3. In the region of the p-well 3, energy is imparted to the carries to produce hot carriers which are then injected into the floating gate 6 thus writing a data.</p>
申请公布号 JPH0878546(A) 申请公布日期 1996.03.22
申请号 JP19940207768 申请日期 1994.08.31
申请人 TOSHIBA CORP 发明人 SATO SHINJI;ARITOME SEIICHI;SHIMIZU KAZUHIRO
分类号 H01L21/8247;H01L27/115;H01L29/788;H01L29/792;(IPC1-7):H01L21/824 主分类号 H01L21/8247
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