| 摘要 |
<p>PROBLEM TO BE SOLVED: To support asynchronous data communication as well as synchronous data communication by performing 0 bit insertion, NRZI and flash, and pulse encoding to bring about such sufficient transition in data that the demodulation side can maintain synchronization independently. SOLUTION: When detecting five continuous '1' bits in a data string, a serial controller 9 inserts a '0' bit and performs NRZI encoding to output transmission data 11. A DFF 10 samples this output, and an XNOR gate 12 generates a pulse when data 11 is changed between two clocks. By this pulse, a 4 counter 13 generates output pulses of 2/16 to 8/16 one-bit cell width in accordance with the bit speed of data 11 and outputs them from a NAND gate 14. A synchronized expansion pulse outputted from a latch 15 by this output is used to generate an IR flash pulse from an IR generator 16 at each transition of the NRZI signal. Thus, a DPLL on the reception side maintains synchronization independently, and asynchronous and synchronous data communications are possible.</p> |
