DOUBLE MAKING PROCESSOR

摘要

The apparatus comprises an error sensing/processing apparatus on an operation part and the same on a stand-by part. The apparatus on the operation part comprises: a data and address-buffering means(21) transmitting data and address to the operation part; a buffer control means(22) which outputs a buffer control signal to the buffering means(21) and outputs a control signal to the stand-by part; an address latch means(26) which latches the next address after receiving a transmission-verifying signal, and maintaining the present address if receiving an error signal; a mode control means(24) controlling the doubling operation type; a main processor-inspecting means(25) inspecting a main processor; an error-sensing and processing means(27) outputting an error signal and an error interrupt signal; and a data transmission-verifying means(23) which outputs a transmission-verifying signal if receiving a write completion signal, and outputs an error signal otherwise.