| 摘要 |
<p>PROBLEM TO BE SOLVED: To enable execution of correct write-in and erasure for a large number of nonvolatile memory cells by a method wherein a pulse oscillating in the positive and the negative is impressed on a floating gate of one or more memory cell transistors of interest of which the addresses are specified. SOLUTION: In a memory cell array 1a/1b, a bit line selecting transistor Tsa1/Tsb1 connects a main bit line BLa1/B1b1 to a sub-bit line BLsa1/B1sb1 selectively. Drains of nonvolatile transistors Ma1 and Ma2/Mb1 and Mb2 are connected to the sub-bit line BLsa1/BLsb1. A bit line capacitor Ca1/Cb1 connected between a common source circuit of memory cell transistors and the sub-bit line is contained in the array. Each nonvolatile memory cell transistor has an N-channel MOS transistor structure equipped with a control gate and a floating gate and nonvolatile charge information is held in each floating gate.</p> |
