SEMICONDUCTOR MEMORY DEVICE

摘要

PROBLEM TO BE SOLVED: To obtain a semiconductor memory which can be accessed at higher rate. SOLUTION: The semiconductor memory comprises a first data path FIRSTDATAPATH connected with a bit line through a column select gate in order to receive and amplify a data through an I/O sense amplifier, a second data path SECONDDATAPATH receiving data on the first data path, transmission gates 36, 38 being conducted selectively by a control signal to transmit data on the second data path, a third data path THIRDDATAPATH having a latch circuit 40 for the data being transmitted by the transmission gate, a fourth data path FOURTHDATAPATH receiving data on the third data path through a repeater 42, a data output buffer 44 generating an output data from data on the fourth data path, a transmission gate 46 inserted between the fourth data path and the data output buffer and being conducted in response to a predetermined control signal(CAS), and a latch circuit 48 for the data being transmitted by the transmission gate. This arrangement realizes high speed access in EDO mode.