DIGITAL SIGNAL PROCESSOR

摘要

PROBLEM TO BE SOLVED: To easily judge the synchronization of the arithmetic operation of a digital signal processing. SOLUTION: A synchronizing signal generating circuit 12 generates the internal identification signal LRI synchrinized with a channel identification signal LRE and a window pulse WD specifying a fixed period including the timing of the rising of the internal identification signal LRI. A digital signal processing circuit 11 fetches digital data DA1 in responce to the internal identification signal LRI to generate digital data DA2 interpolated by a prescribed arithmetic processing. A synchronization judging circuit 13 judges whether the rising of the channel identification signal LRE is within the specified period of the window pulse WD or not and when the rising of the channel identification signal LRE is out of the specified period, the circuit 13 raises a reset pulse RST to reset the synchronizing signal generating circuit 12.