| 摘要 |
<p>PROBLEM TO BE SOLVED: To prevent ground potential fluctuation due to simultaneous discharge of plural word lines by delaying the selective operation of the word line when a vertically piled memory cells group connected in series is switched to non- selection. SOLUTION: For instance, when the memory cell MC11 is selected from the memory cell MC21 to be switched, by that a vertically piled block selection signal XS1 and a word selection signals XM2-n are made an 'L', and the word selection signal XM1 is made an 'H', the word line W10 of the selected memory cell MC11 is selected. Since the vertically piled memory cells group containing the memory cell MC21 becoming the non-selection makes the vertically piled selection signal XSn the 'H', plural word lines W20 discharge simultaneously. At this time, a resistor R1 is inserted into a drain of an NMOS transistor Q2 constituting NOR gates 31-n, 41-n, and non-selective operation by the vertically piled selection signals XS1-n are delayed, and the discharge time by switching the word line is delayed.</p> |
