Speicherzellenfeld

摘要

A memory cell array comprises word lines WL1-WLM, memory cells MCC, MCD each having a gate electrode connected to the word lines, bit lines BL1-BLN which cross with the word lines, source lines SL1-SLK to which each source electrode of the memory cells is connected, a first decoder 1 connected to odd numbered source lines SL1, SL3 for applying a bias voltage to the odd numbered source lines and a second decoder 2 connected to even numbered of source lines SL2, SLK for applying a bias voltage to the even numbered source lines. The memory cell array has floating gate transistors and enables electrical programming and erasure. A further aspect relates to a memory cell array having floating gate memory cells forming a basic cell group, combined horizontally and longitudinally, in which four cells (100, 200, 300, 500 Fig 4) form a single group having a drain in common. In a still further aspect a basic cell group of four units cells are combined horizontally and longitudinally and have a single bit line contact in common (22, Fig 5). A semiconductor construction of the basic cell group including the first (12A, Figs 5-11B) to fourth (12D) floating gates is described.