发明名称 DIGITAL COMPENSATION TYPE A/D CONVERTER
摘要 <p>PROBLEM TO BE SOLVED: To attain more accurate digital compensation by operating a selection means, a sample-and-hold means, an A/D converter and a digital compensation means or the like in response to a clock signal so as to generate a calibration value thereby repeating conversion process of a normal operation again and calculating a calibration value with higher resolution. SOLUTION: A selection means 10 is made up of a multiplexer selecting an input signal and a sample-and-hold means 12 samples the signal in response to a signal Q1 and holds the signal. A multi-bit A/D converter 18 configures again the hold signal to provide the output of an analog re-configuration signal Vb. An adder means 24 adds a digital correction signal and a digital compensation signal. A control means 28 controls the resolution of a calculated compensation signal to be detected as a compensation signal with a higher resolution than that in the normal operation and stores the signal to a digital compensation means 22. A digital compensation means detects a signal with high resolution by processing calculation data of the calibrated value.</p>
申请公布号 JPH09186591(A) 申请公布日期 1997.07.15
申请号 JP19960204542 申请日期 1996.08.02
申请人 SAMSUNG ELECTRON CO LTD 发明人 RI SEIKOU;SOU RITSUKOU
分类号 H03M1/06;H03M1/10;H03M1/12;H03M1/46;(IPC1-7):H03M1/10 主分类号 H03M1/06
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