| 摘要 |
A bus interface circuit between different kinds of equipments having a S bus interface controlling synchronous S bus; a VME bus interface controlling asynchronous VME bus; a buffer according data of said two buses with the transmitting unit of address; a buffer controller controlling input/output of said buffer; and a data exchanger exchanging data to accord data size from said S bus interface to said VME bus interface is disclosed. Thereby, it is possible to output single or block data inputted to S bus to VME bus in shortest time in contacting S bus and VME bus. |
