| 摘要 |
PROBLEM TO BE SOLVED: To provide an anlog multiplier capable of correcting phase errors due to circuit delay. SOLUTION: Two input signals S1 and S2 to be multiplied are respectively inputted through a single balance conversion circuit SBC to a multiplication core MT and output signals S3 are obtained. At the time, a phase difference is generated between the input signals S1 and S2 and the output of the output signals S3 declines, however, in order to prevent it, a capacitor C is put in the single balance conversion circuit SBC and the phase difference of the input signals S1 and S2 is eliminated. |
