| 摘要 |
PURPOSE:To allow the subject device to meet an incompatible requirements of a high resolution and tracing to a change in the property of an input signal by adopting a variable block length. CONSTITUTION:A signal fed to an input terminal 1 is stored tentatively in a buffer 19 and linear transformation is applied to the signal by a linear transformations circuit 3. An error calculation circuit 9 calculates the error by using signals before linear transformation and after linear transformation. When the calculation of errors to block lengths N1, N2, N3, N4-Nn are all finished, an error comparator 11 detects an optimum block length giving a minimum error and gives the result to a selection multiplexing circuit 20. The selection multiplexing circuit 20 stores the output of a quantizer 4 corresponding to each block length and the output of a bit distribution circuit 6, selects a value corresponding to the optimum block length supplied later, multiplexes the value with the optimum block length and the result is sent to a transmission line 12. |
