| 摘要 |
PROBLEM TO BE SOLVED: To suppress malfunctions due to the timing deviation of line detection signals by providing a synchronizing signal correction circuit for correcting the omission part of synchronizing signals equivalent to the clock input signals of a counter circuit and detecting several lines in front and at the back of the line to which EDTV2 identification signals are inserted. SOLUTION: The counter circuit 6 starts counting synchronization correction signals J generated from half H elimination signals D by the synchronizing signal correction circuit 8 after being reset by vertical synchronization delay signals F. In this case, when the omission of signals is generated in the half H elimination signals D, the signals J detect that the omission part is present in the halt H elimination signals D when the next rise is not inputted within 65μs for instance from the rise of the half H elimination signals D by the circuit 8. Then, by adding pulses to the omission part of the signals D (65μs part from the final rise,) clock signals without the omission are obtained. Thus, the several lines in front and at the back of the line to which the BDTV2 identification signals are inserted are detected and the malfunctions are suppressed.
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