发明名称 VIDEO SIGNAL PROCESSING UNIT
摘要 <p>PROBLEM TO BE SOLVED: To attain high speed processing for the entire compression processing by conducting quantization arithmetic operation at a high speed. SOLUTION: A coefficient extraction and comparison means 103 compares the absolute value of a DCT coefficient from a frequency conversion means 101 with the absolute value of a 2nd coefficient being one half of the 1st coefficient of an original quantization matrix table from a 1st storage means 102. When the DCT coefficient is smaller than the 2nd coefficient, the DCT coefficient is sent to a 1st arithmetic means 106 by a switch 105, and 0 is substituted in place of the DCT coefficient. When the DCT coefficient is larger than the 2nd coefficient, the DCT coefficient is fed to the 2nd arithmetic means 107 by the switch 105, the coefficient is divided by a 1st coefficient from a 2nd storage means 108 and rounded off. Outputs of the 1st and 2nd arithmetic means 106, 107 are fed sequentially to a quantization coefficient generating means 109, from which a block after quantization is obtained.</p>
申请公布号 JPH09307901(A) 申请公布日期 1997.11.28
申请号 JP19960117368 申请日期 1996.05.13
申请人 TOSHIBA CORP 发明人 YAMADADERA SHINJI
分类号 H04N19/60;H03M7/30;H04N19/124;H04N19/136;H04N19/176;H04N19/196;H04N19/423;H04N19/625;(IPC1-7):H04N7/30 主分类号 H04N19/60
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