Maintaining stress in a layout design of an integrated circuit having fin-type field-effect transistor devices

摘要

A computer-implemented method for maintaining stress in an integrated circuit having fin-type field-effect transistor devices includes selecting, by a processor of a computer system, a representation of an initial layout design for the integrated circuit, the layout design having design shapes including existing fin shapes; adding, by the processor of the computer system, a fin shape to one or more of the existing fin shapes to merge the one or more existing fin shapes with another existing fin shape to form an extended fin shape; adding, by the processor of the computer system, gate contacts to gates which intersect the added fin shape to generate a modified layout design; and saving the modified layout design to a memory communicatively coupled to the processor of the computer system, where device operation of the initial layout design for the integrated circuit is maintained in the modified layout design for the integrated circuit.

主权项

1. A computer-implemented method for maintaining stress in an integrated circuit having fin-type field-effect transistor devices, the method comprising:
selecting, by a processor of a computer system, a representation of an initial layout design for the integrated circuit, the layout design having design shapes comprising existing fin shapes; adding, by the processor of the computer system, a fin shape to one or more of the existing fin shapes to merge the one or more existing fin shapes with another existing fin shape to form an extended fin shape; adding, by the processor of the computer system, gate contacts to gates which intersect the added fin shape to generate a modified layout design, saving the modified layout design to a memory communicatively coupled to the processor of the computer system, wherein device operation of the initial layout design for the integrated circuit is maintained in the modified layout design for the integrated circuit, and forming the modified layout design in an integrated circuit.