发明名称 PICTURE SYNTHESIZER
摘要 PROBLEM TO BE SOLVED: To reduce the number of line buffers. SOLUTION: Main and subpicture signals S1 and S2 are converted into main and subpicture signals P1 and P2 after a thinning by thinning sections 1 and 2. The signals P1 and P2 are properly distributed and written into line buffers A, B and C by a multiplexer 5. The written signals P1 and P2 are properly selected by a multiplexer 6 and are written into a DRAM 10. The before one field signals P1 and P2 are read from the DRAM 10 in the order in which the picture signals are displayed in parallel on a same screen and are outputted as synthesized picture signals S3. By providing the multiplexer 5, foure line buffers required for writing into the DRAM 10 in a conventional device are reduced to three line buffers.
申请公布号 JPH1074075(A) 申请公布日期 1998.03.17
申请号 JP19960231912 申请日期 1996.09.02
申请人 MEGA CHIPS:KK 发明人 ISHIO YASUSHI
分类号 H04N5/265;G06T1/00;G06T3/00;G09G5/00;G09G5/14;G09G5/36;G09G5/397;G09G5/399;H04N5/45;(IPC1-7):G09G5/14 主分类号 H04N5/265
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