发明名称 A system level mechanism for invalidating data stored in the external cache of a processor in a computer system
摘要 <p>A computer system is disclosed including a memory subsystem and a processor subsystem having an external cache and an external mechanism for invalidating cached datablocks in the processor subsystem and for reducing false invalidation operations . The processor subsystem issues a write invalidate message to the memory subsystem that specifies a datablock and that includes an invalidate advisory indication that indicates whether the datablock is present in the external cache. The invalidate advisory indication determines whether the memory subsystem returns an invalidate message to the processor subsystem for the write invalidate operation. <IMAGE></p>
申请公布号 SG50950(A1) 申请公布日期 1998.07.20
申请号 SG19960006437 申请日期 1996.03.29
申请人 SUN MICROSYSTEMS, INC. 发明人 NISHTALA SATYANARAYANA;EBRAHIM ZAHIR;LOO VAN, WILLIAM, C.;NORMOYLE, KEVIN, B.;KOHN LESLIE;COFFIN, LOUIS F., III
分类号 G06F12/08;(IPC1-7):G06F12/08;G06F15/167 主分类号 G06F12/08
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