发明名称 ERASING METHOD OF FLASH MEMORY CELL AND DEVICE THEREFOR
摘要 <p>PROBLEM TO BE SOLVED: To reduce a time for an erasing operation and a peak current by a method wherein a drain bias voltage for erase is impressed on a certain sector and a prescribed time later the drain bias voltage for erase is impressed on the subsequent sector for erasing, in a manner of overlapping each other. SOLUTION: After a prescribed delay time (t1) passes after a control gate bias voltage is supplied to a first sector, the control gate bias voltage is supplied to a second sector. Although the time points of supply of the control gate bias voltage to the first sector to an (n)th sector are different, erasing operations of the first to (n)th sectors overlap each other for a prescribed time respectively. In other words, the second sector starts the erasing operation before the erasing operation of the first sector is completed, and a third sector starts the erasing operation before the second sector completes the erasing operation.</p>
申请公布号 JPH10199271(A) 申请公布日期 1998.07.31
申请号 JP19970370260 申请日期 1997.12.26
申请人 HYUNDAI ELECTRON IND CO LTD 发明人 PARK JOO ON;BOKU KEIRAI
分类号 G11C16/02;G11C16/06;G11C16/16;(IPC1-7):G11C16/02 主分类号 G11C16/02
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