| 摘要 |
In a multi-value modulation system such as M bits/1 symbol, a pattern matching apparatus is arranged by a coincident bit number detecting circuit (3,7,13,19,25) for detecting a coincident bit number between a reception symbol and the known pattern owned by a receiver within 1 symbol; a delay circuit (5, 11, 17, 23) for delaying a detection result; and an adder (9, 15, 21, 27). Then, a coincident bit number between the received 1 symbol (M bits) and 1 symbol (M bits) of the know pattern is detected This detected bit number is added to each other, so that when a length of a UW pattern is N bits, the total number of adders can be reduced to N/M.
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