| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide an intensive wiring system with small circuit scale and to flexibly cope with various communication systems by constituting the system of an FPGA whose circuit structure is capable of being changed by changing connection information between circuits. SOLUTION: When the need to transmit an arithmetic operation result of an MPU 101 to other nodes arises and data to be transmitted is judged to be transmitted by a communication bus A, a request signal to rewrite a communication control circuit 134 of the FPGA 103 to the communication bus A is outputted to a logic circuit data conversion control circuit 133. When the request signal is inputted, the connection information of memory 102 is read in, the communication control circuit 134 is rewritten for the communication bus A and a rewriting completion signal is outputted for the MPU 101. When the rewriting completion signal is inputted, a transmission processing is completed by writing the data to be transmitted to a transmission register of the communication control circuit 134 in the transmission processing of the MPU 101. The transmission data is outputted to the communication bus A through a driver 104 for the communication bus A with a rewritten control circuit for the communication bus A by the communication control circuit 134.</p> |
