发明名称 UTOPIA LEVEL 2 POLLING CONTROL SYSTEM
摘要 <p>PROBLEM TO BE SOLVED: To minimize lowering of performance between an ATM layer function and a PHY layer function by being provided with a PHY number conversion register function, a PHY number conversion register writing function and a confliction mediation function. SOLUTION: A write request 18 is transmitted with set PHY number data 14 to be set in a PHY number conversion function 5 and a set PHY number address 15 by the PHY number conversion register writing function 4. The contents corresponding more to a PHY number conversion register address 17 are read from memory by the PHY number conversion register function 5. A PHY number write instruction 19 is activated only when the least significant bit of counter information 16 is '0' and the write instruction 18 is active by the confliction mediation function 6. The maximum PRY number capable of being treated by an ATM layer function 100×2 is counted by a polling maximum synchronization counter 7 and the PHY number is always counted up by a UTOPIA clock.</p>
申请公布号 JPH1127276(A) 申请公布日期 1999.01.29
申请号 JP19970175400 申请日期 1997.07.01
申请人 NEC CORP;NEC ENG LTD 发明人 IWAI KAZUHIRO;KAWABATA HIROMI
分类号 H04Q3/00;H04L12/28;(IPC1-7):H04L12/28 主分类号 H04Q3/00
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