发明名称 DEVICE AND METHOD FOR ENCODING AND IMAGE PROCESSOR
摘要 <p>PROBLEM TO BE SOLVED: To reduce the scale of a circuit and to attain cost reduction and power conservation by providing a code amount estimate circuit with a one- block code amount calculation circuit corresponding to S kinds of quantizing characteristics and an Nblock code amount adder circuit corresponding to P kinds of quantizing characteristic numbers. SOLUTION: At the code amount estimate circuit, one-block code amount calculation circuits 2600 -260S-1 corresponding to S kinds of quantizing characteristics calculate the amount of codes for one pixel block by quantizing the data of one pixel block, to which DCT is performed, while using quantizing tables 0 to S-1. N-block code amount adder circuits 2080 -208P-1 add the code amounts respectively selectively supplied from a code amount selector circuit 207 for N pixel blocks. A code amount discrimination circuit 209 supplies the quantizing characteristic number, which is the quantizing characteristic of the least picture quality degradation less than the prescribed code amount, from the code amount for N pixel blocks with supplied quantizing characteristic numbers 0 to P-1 to a quantizing circuit 105.</p>
申请公布号 JPH1141599(A) 申请公布日期 1999.02.12
申请号 JP19970195775 申请日期 1997.07.22
申请人 CANON INC 发明人 IKEDA SHINGO
分类号 H04N5/92;H03M7/30;H03M7/40;H04N1/41;H04N19/12;H04N19/126;H04N19/132;H04N19/134;H04N19/136;H04N19/149;H04N19/176;H04N19/18;H04N19/196;H04N19/20;H04N19/42;H04N19/46;H04N19/60;H04N19/625;H04N19/70;H04N19/85;(IPC1-7):H04N7/30 主分类号 H04N5/92
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