| 摘要 |
A cross-connect comprises a cross-connecting processor, control memory, data memory and a plurality of transmitter interfaces. It is arranged so as to read instructions from the control memory and, in response to the reading of a certain first instruction from the control memory, to read certain data from the data memory and connect said data to a certain transmitter interface. In addition, the cross-connecting processor is arranged so as to set said transmitter interface to a high-impedance state in response to the reading of a certain second instruction from the control memory. Said second instruction includes a certain first block number which does not indicate any block in the frame structure of the cross-connecting bus used in the cross-connect. |
