发明名称 INTERRUPT SYSTEM
摘要 <p>The present invention is related to a data handling system comprising a central processing unit for executing a sequence of commands stored in a memory. This central processing unit comprises an interrupt request input and a priority input as well as means for servicing an interrupt request by executing a command sequence at a predefined address in said memory. The predefined address is an interrupt base address plus an offset address value defined by a priority number provided at the priority input. The system further comprises an interrupt request control unit comprising interrupt arbitration means and generating, after determining the interrupt request, the highest priority by said interrupt arbitrationmeans, an interrupt request signal fed to said interrupt request input and providing a priority number at said priority input. A plurality of peripheral devices each having an associated interrupt service register for storing a priority number is coupled with the interrupt request control unit via an interrupt arbitration bus.</p>
申请公布号 WO1999014679(A1) 申请公布日期 1999.03.25
申请号 US1998018671 申请日期 1998.09.04
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