| 摘要 |
<p>PROBLEM TO BE SOLVED: To prevent the throughput of a system from being damaged while reducing power consumption by performing shared memory access at optimum access time even at the time of the low-speed operation of a processor at a low working rate. SOLUTION: Under the control of a bus control circuit 2a, a processor 1a enables access through a common bus 8 to a shared memory 7. Even while the processor 1a is operated by a low-speed clock in a low power consumption mode, the operation is performed while being switched to a high-speed clock only at the time of accessing the shared memory 7 so that the waiting time can be minimized even when the shared memory access is competed with the other processor. Besides, the operation of a clock switching circuit 2b is similar to the operation of a clock switching circuit 2a as well and even concerning the processor 1b, even when the processor 1b is operated by the low-speed clock in the low power consumption mode, the operation is performed by the high-speed clock at the time of accessing the shared memory so that the waiting time in access competition can be minimized.</p> |
