发明名称 ATM SWITCH
摘要 <p>PROBLEM TO BE SOLVED: To correspond to the increase/decrease of the number of input/output terminals, to speed up a processing and to enlarge a scale by dispersively arranging plural access modules and dispersively executing the processing without executing contention arbitration control and arbitration. SOLUTION: Cells arriving at input terminals 1-1 to 1-4 are distributed to output terminals 2-1 to 2-4 in accordance with destinations and they are transmitted to a signal line 6 through n-pieces of access modules 7-1 to 7-4. Respective access modules are provided with the timing controllers of reception and transmission and a synchronizing signal and a clock signal, which are generated in the synchronous modules 30, are transmitted through signal lines 21 and 20. Reception timing and transmission timing are sequentially set to them. Reception timing and transmission timing are equally allocated to respective access modules. The length of reception timing is set to be N-1 of the length of transmission timing. Transmission timing is set so that the module to which reception timing is allocated can receive the cell transmitted from the other module.</p>
申请公布号 JPH11112520(A) 申请公布日期 1999.04.23
申请号 JP19970274723 申请日期 1997.10.07
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 YAMANAKA NAOAKI;TAKATANI NAOKI
分类号 H04Q3/00;H04L12/28;(IPC1-7):H04L12/28 主分类号 H04Q3/00
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