发明名称 ARITHMETIC CIRCUIT
摘要 PROBLEM TO BE SOLVED: To reduce an output error when a denominator input signal becomes small by amplifying a denominator signal and a numerator signal by changing the amplification of an amplifier circuit so that the size of the denominator input signal lies within the range for the normal operation of a dividing circuit. SOLUTION: A circuit block A supplies a denominator input Y and a numerator input X to a dividing circuit (h). A comparator (e) compares a denominator input limit value (m) supplied from a reference signal input terminal (m) with an input signal (j) on the denominator input side, and when the input signal (j) becomes smaller than a reference voltage, an outputαis turned on. When the outputαof the compartor (e) is off, switches SW1-SW4 are positioned in the shown figure, and the gains of amplifier circuits (f) and (g) are obtained as normal gains. When the outputαof the comparator (e) is on, the switches SW1-SW4 are switched, and the gains of the amplifier circuits (f) and (g) become smaller.
申请公布号 JPH11175646(A) 申请公布日期 1999.07.02
申请号 JP19970335874 申请日期 1997.12.05
申请人 SONY CORP 发明人 OKAMATSU KAZUHIKO
分类号 G06G7/16;G11B7/09;(IPC1-7):G06G7/16 主分类号 G06G7/16
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