发明名称 SEMICONDUCTOR MEMORY DEVICE
摘要 <p>PROBLEM TO BE SOLVED: To provide a semiconductor memory device which reduces a parasitic capacitance affecting a maximum generation voltage value, which can generate a high negative voltage internally and in which a generated high voltage can be measured by all testers. SOLUTION: A memory matrix, its peripheral circuit and the like constitute a 256-M flash memory which is required to generate a high negative voltage internally. In an internal power-supply circuit in the peripheral circuit, a negative-voltage boosting circuit which uses another negative voltage and which generates a negative high voltage by boosting the negative voltage by a single- stage capacitance is contained, and a limiter circuit which controls the negative high voltage to be a set voltage, which judges whether the negative high voltage is generated normally and by which a signal at an external voltage amplitude is outputted to the outside, is contained. On the basis of the output signal of the limiter circuit, the boosting operation of the negative-voltage boosting circuit is performed. A boosting circuit 22 in the negative-voltage boosting circuit uses a boosting system by a single-stage capacitance. A maximum generation voltage value is not dropped due to the influence of a parasitic capacitance.</p>
申请公布号 JP2000011675(A) 申请公布日期 2000.01.14
申请号 JP19980181811 申请日期 1998.06.29
申请人 HITACHI LTD;HITACHI ULSI SYSTEMS CO LTD 发明人 HARADA TOSHINORI;KUBONO SHOJI
分类号 G11C16/06;H02M3/07;(IPC1-7):G11C16/06 主分类号 G11C16/06
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