| 摘要 |
<p>PROBLEM TO BE SOLVED: To correct the duty ratio of a signal to be 1:1 without giving influence on the operation of a PLL circuit or a DLL circuit. SOLUTION: A rising timing control circuit 1a generates a signal S10 obtained by inverting the signal S6 and a time required for transition from high to low in the signal S10 is changed. The transition of the signal S2 is executed when the signal S10 becomes lower than a reference value Vref by a comparator A1 and the duty ratio of the signal S2 is changed by the length of a falling time. Besides, a duty ratio detecting circuit 2 is a charge pump for drawing and outputting a fixed quantity of current in accordance with the value of the voltage of the signal S2 and a duty ratio correcting filter 3 converts the signal S8 from the duty ratio detecting circuit 2 into a flat voltage signal S9. The voltage signal S9 is adopted as a feedback signal to the rising timing control circuit 1a so that the duty ratio of the signal S2 is corrected to be 1:1.</p> |
