| 摘要 |
PURPOSE: A BIST(built in self test) circuit having a debugging function is provided to perform a debugging by receiving selectively an input for debugging when a semiconductor integrated circuit is tested. CONSTITUTION: A BIST(built in self test) circuit having a debugging function comprises a parallel random pattern generator(10), on more scan chains(13,14,15), and MISR(multiple input signature register)(16,20). The parallel random pattern generator generates a test data pattern to test a combination logic block(11,12). The scan chains inputs the test data pattern to the combination logic block. Also the scan chain receives and stores a response data output from the combination logic block. The MISR receives selectively one of the outputs from the scan chins and compresses the received data.
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