发明名称 DIGITAL CHANNELIZER HAVING EFFICIENT ARCHITECTURE FOR CYCLICSHIFTING AND METHOD OF OPERATION THEREOF
摘要 The invention is a digital channelizer and a process for dividing an input bandwidth into at least some of N channels. A digital channelizer which divides an input bandwidth into at least some of N channels in accordance with the invention includes a window presum (102), responsive to I input groups of data words, having I signal processing paths and outputting I groups of output data words, each input group of data words being processed in a different one of the I signal processing paths and individual channels of at least some of the N channels being decimated by a decimation factor of M; a cyclic shift (24'), coupled to the I output groups of data words, having I cyclic shift paths, each cyclic shift path being responsive to a different output group of data words to produce I output groups of data words, each cyclic shift path comprising a plurality of word shifting elements each responsive to a group of data words; and a discrete Fourier transform (26') coupled to the I output groups of cyclically shifted data words outputted from the cyclic shift, which performs a discrete Fourier transform on the I output groups of the cyclically shifted data words to produce at least some of the N channels; and wherein I equals GCD(N,M) and each output group of cyclically shifted data words is repeatedly shifted through a number of cycles equal to N/GCD(N,M) with each cycle having a shift value defined by mM*modulo N, or -mM*modulo N and m being an index variable ranging from zero upward to positive numbers.
申请公布号 CA2298999(A1) 申请公布日期 2000.08.26
申请号 CA20002298999 申请日期 2000.02.18
申请人 TRW INC. 发明人 CASO, GREGORY S.;MORETTI, VINCENT C.
分类号 G01R23/16;G06F17/14;H03H17/00;H03H17/02;H04J1/00;H04J11/00;H04L5/06;(IPC1-7):H04J1/08;H04J1/05 主分类号 G01R23/16
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