发明名称 VARIABLE DELAY CIRCUIT
摘要 <p>PROBLEM TO BE SOLVED: To change a delay characteristic of a variable delay circuit by blowing out fuses. SOLUTION: A plurality of delay paths 20-1-20-n to which a node N1 is connected in common via an input terminal IN have delay characteristics in response to number of inverters 21. Connection selection circuits 30-1-30-n are respectively provided between nodes N2 of the delay paths 20-1-20-n and an output terminal OUT. A delay path having a desired delay characteristic is selected and connected to the output terminal OUT by properly blowing out fuses in the connection selection circuits 30-1-30-n.</p>
申请公布号 JP2000278102(A) 申请公布日期 2000.10.06
申请号 JP19990085413 申请日期 1999.03.29
申请人 OKI ELECTRIC IND CO LTD 发明人 KATO JOJI
分类号 H03H9/30;H03K5/13;(IPC1-7):H03K5/13 主分类号 H03H9/30
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