发明名称 Method and apparatus for implementing predicated sequences in a processor with renaming
摘要 Systems, apparatus, and methods are disclosed for generating pairs of conditional instructions corresponding to special predicate sequences from single instructions having a predicate. These pairs of conditional instructions update a destination register regardless of the truth or falsity of the predicate. The destination register is renamed to a new physical location. In this manner, register renaming can be used with predicate sequences to gain performance efficiencies and to overcome limitations of the prior attempted approaches.
申请公布号 US6170052(B1) 申请公布日期 2001.01.02
申请号 US19970002016 申请日期 1997.12.31
申请人 INTEL CORPORATION 发明人 MORRISON MICHAEL J.
分类号 G06F9/30;G06F9/32;G06F9/38;(IPC1-7):G06F21/06 主分类号 G06F9/30
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