发明名称 EDGE PASSIVATION JUNCTION TERMINAL EXPANSION WITH TWO SLOPE OF SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To increase a power semiconductor device in breakdown voltage by a method wherein an electric field at the active area-JTE junction is lessened in intensity. SOLUTION: A silicon semiconductor die 400 is equipped with a heavily doped silicon substrate and an upper layer possessed of a first conductivity-type doped silicon formed on the substrate. The upper layer 101 is equipped with a second conductivity-type well region 102 opposite to the first conductivity, and an edge passivation zone equipped with a junction terminal expansion(JTE) depletion region 403, where the depletion region 403 is provided with an extension 406 which is separate from the well region 102 and extends under it. The depletion region 403 is varied in dopant concentration and gets maximum at a point 404 substantially located just under its junction with the well region 102. The depletion region 403 is more reduced in dopant concentration at parts 405 and 406 which extend under the well region 102 starting from the point 404.
申请公布号 JP2001077347(A) 申请公布日期 2001.03.23
申请号 JP20000219475 申请日期 2000.07.19
申请人 INTERSIL CORP 发明人 BRUSH LINDA;NEILSON JOHN
分类号 H01L29/73;H01L21/31;H01L21/331;H01L29/06;H01L29/74;H01L29/78;H01L29/861;(IPC1-7):H01L29/06 主分类号 H01L29/73
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