ADDRESS DATA GENERATION CIRCUIT AND METHOD FOR MULTISTAGE INTERLEAVING

摘要

PROBLEM TO BE SOLVED: To reduce the circuit scale and to downsize a device by reducing the memory capacity in an address data generation circuit for multistage interleaving. SOLUTION: Respective stages including a final stage, an intermediate stage, and a 1st stage each equipped with a holding circuit which holds an interleaving pattern as a minimum unit and arithmetic circuits for multiple stages find interleaving patterns sequentially in steps to find the address data of an interleaving pattern corresponding to desirable data to be addressed finally. The clocks of access circuits of the holding circuits which holds the interleaving patterns of the respective stages and respective arithmetic circuits are synchronized to generate the patterns without storing the arithmetic results of the respective stages in a storage means.